Description:

VL82C481 System/Cache/ISA bus Controller

The VL82C481 supports the Weitek 4167 Numeric Coprocessor.

The memory controller logic is capable of accessing up to 64 MB. There can be up to four banks of 256K, 1M, or 4M DRAMs used in a system. The VL82C481 can drive two banks without external buffering. Built-in Page Mode operation and up to two-way interleaving allows the PC designer to maximize system perform- ance using low-cost DRAMs. Programmable DRAM timing is provided for RAS# pre- charge, RAs-to-CAS delay, and CAS# pulse width.

The VL82C481 write-back cache controller logic supports one or two bank direct map write-back cache with external tag storage. The cache controller can perform 2-1-1-1 reads with two banks or 2-2-2-2 reads with one bank. It can also perform 3-2-2-2 cycle reads for support of slower SRAMs at higher frequences. The VL82C481 can perform one wait state writes on cache-hits. An optional zero wait state write mode is provided for use with fast cache SRAMs. The cachable DRAM range includes 2 MB up to 64 MB utilizing cache data SRAM sizes of 32 KB through 1 MB, respectively.

The HITM# input is provided to force the VL82C481 to abort DRAM or cache cycles when a hit on a dirty line in the CPU write-back cache is detected. the DRAM or cache cycle is subsequently restarted after the CPU has written back the dirty data.

The VL82C481 can be programmed for asynchronous or synchronous operation of the ISA bus.

The VL82C481 also performs all the data buffer control functions required for a 486-based ISA bus system. Under the control of the CPU, the VL82C481 routes data to and from the CPU's local D bus, the internal XD bus, and the slots (SD bus). During CPU ISA bus reads, the data is latched for synchronization with the CPU. Parity is checked for D bus DRAM read operations. On power-on default, the chip does not generate parity for CPU writes to DRAM, but does generate cache write- back cycles. However, a mode is provided in which the VL82C481 will generate parity during either CPU writes or VL master writes. Even parity is generated and checked.

Features:

• Fully compatible with 486-based ISA bus systems
• Power-on reset option selects various operational modes
• Up to 40 MHz CPU operation
• Includes full support for CPU's with internal write-back cache (P24T, etc.)
• Comprehensive VESA VL-Bus support
• Replaces the following peripheral logic on the motherboard:
  • Two 82C37A DMA controllers
  • 74LS612 memory mappers (extended to support 64 MB)
  • Two 82C59A interrupt controllers
  • 82C54 timer
  • 82284 clock generator and ready interface
  • 82288 bus controller
• Memory controller features include:
  • Up to 64 MB system memory
  • One to four banks 32 bits wide
  • 256K, 1M or 4M DRAM
  • Double-sided SIMMs
  • Page Mode DRAM access
  • Two-way interleave support
  • Programmable RAS#/CAS# timing
  • Burst read and write support
  • Parity generation/checking for on-board DRAM
  • Staggered RAS# refresh
• Supports:
  • 8- or 16-bit wide BIOS ROM
  • Shadow RAM in the 640K-1M area
  • Asynchronous ISA bus operation up to 16 MHz
  • Relocation of slot ROMs
  • Access to devices residing on the local bus
  • Weitek 4167 numeric coprocessor
• Includes:
  • Memory/refresh controller
  • Port A, B, and NMI logic
  • Bus steering logic
  • Turbo control
  • hidden refresh
  • Three-stateable outputs for board testing
• Selectable slow DRAM refresh saves power
• On-chip write-back cache controller:
  • External tags
  • Direct map
  • Separate "dirty" RAM not required
  • 2-1-1-1 reads with two banks, 2-2-2-2 with one bank
  • 32 KB to 1MB cache size
  • One wait state writes on cache-hits
  • Optional zero wait state writes supported
  • Optional one wait state reads supported
• Other features:
  • Programmable for 10- or 16-bit internal I/O addressing
  • Programmable drive on the DRAM and ISA bus signals
  • Programmable memory access to define "fast-bus", local bus, slot bus, non-cacheable and write-protect areas
  • Input pin defines access to local bus devices
  • Optional keyboard command blocking for fast A20GATE and CPU reset
• 0.8-micron CMOS technology
• 208-lead MQFP (metric quad flat pack) 0 to 70 degrees C operating temperature